1. Field of the Invention
The invention relates generally to complementary metal oxide semiconductor (CMOS) structures. More particularly, the invention relates to CMOS structures with enhanced performance.
2. Description of the Related Art
Field effect transistors (FETs) are frequently used as switching devices or signal processing devices within semiconductor circuits. In order to provide for decreased power consumption, field effect transistors are frequently fabricated within the context of a complementary doped (i.e., including an n conductivity type dopant and a p conductivity type dopant) pair of field effect transistors that is typically referred to as a complementary metal oxide semiconductor (CMOS) structure.
Recent advances in field effect transistor structure and device fabrication have centered on the use of mechanically stressed layers within field effect transistor structures to provide mechanically strained channel regions within the field effect transistor structures. In turn, the mechanically strained channel regions are intended to provide for enhanced charge carrier mobility within field effect transistor devices. Typically, within the context of conventional crystallographic orientations of semiconductor substrates that are used for fabricating field effect transistor structures, a tensile channel strain is desirable for enhanced electron charge carrier mobility within an n-FET device channel, while a compressive channel strain is desirable for enhanced hole charge carrier mobility within a p-FET device channel.
In accordance with the above described desirable FET device polarity based channel strain differences, it is thus clear that complementary doped FET devices within CMOS structures benefit from complementary stress and strain levels. However, such differential stress and strain levels within an n-FET channel in comparison with a p-FET channel are often difficult to efficiently engineer when designing and fabricating a CMOS structure.
Various CMOS structures having enhanced performance, and methods for fabricating the CMOS structures, are known in the semiconductor fabrication art. A particular example of an enhanced performance CMOS structure is disclosed within Donaton et al., in “Design and Fabrication of MOSFETs with a Reverse Embedded SiGe (Rev. e-SiGe) Structure,” IEDM Technical Digest, 2006 (use of a silicon-germanium alloy stressor layer within a silicon/silicon-germanium alloy bilayer n-FET channel structure).
Semiconductor structure and semiconductor device dimensions are certain to continue to decrease, while demands for enhanced semiconductor device performance are certain to continue to increase. Thus, desirable are CMOS structures that provide enhanced performance at decreased dimensions, as well as methods for fabricating those CMOS structures.